november 2013 fdp12n50nz / fdpf12n50n z ? n-channel unifet tm ii mosfet ?2010 fairchild semiconductor corporation fdp12n50nz / fdpf12n50nz rev. c1 www.fairchildsemi.com 1 fdp12n50nz / fdpf12n50nz n-channel unifet tm ii mosfet ? 500 v, 11.5 a, 520 m ? features ?r ds(on) = 460 m ? (typ.) @ v gs = 10 v, i d = 5.75 a ? low gate charge (typ. 23 nc ) ? low c rss (typ. 14 pf ) ? 100% avalanche tested ? esd improved capability ? rohs compliant applications ? lcd/led/pdp tv ? lighting ? uninterruptible power supply description unifet tm ii mosfet is fairchild semiconductor?s high voltage mosfet family based on adv anced planar stripe and dmos technology. this advanced mosfet family has the smallest on-state resistance among the planar mosfet, and also pro- vides superior switching per formance and higher avalanche energy strength. in addition, internal gate-source esd diode allows unifet ii mosfet to withstand over 2kv hbm surge stress. this device family is suitable for switching power con- verter applications such as power factor correction (pfc), flat panel display (fpd) tv power, atx and electronic lamp bal- lasts. mosfet maximum ratings t c = 25 o c unless otherwise noted . *drain current limited by maximum junction temperature thermal characteristics symbol parameter fdp12n50nz fdpf12n50nz unit v dss drain to source voltage 500 v v gss gate to source voltage 25 v i d drain current - continuous (t c = 25 o c) 11.5 11.5* a - continuous (t c = 100 o c) 6.9 6.9* i dm drain current - pulsed (note 1) 46 46* a e as single pulsed avalanche energy (note 2) 560 mj i ar avalanche current (note 1) 11.5 a e ar repetitive avalanche energy (note 1) 17 mj dv/dt peak diode recovery dv/dt (note 3) 4.5 v/ns p d power dissipation (t c = 25 o c) 170 42 w - derate above 25 o c 1.37 0.33 w/ o c t j , t stg operating and storage temperature range -55 to +150 o c t l maximum lead temperature for soldering, 1/8? from case for 5 seconds 300 o c symbol parameter fdp12n50nz fdpf12n50nz unit r ? jc thermal resistance, junction to case, max. 0.73 3.0 o c/w r ? ja thermal resistance, junction to ambient, max. 62.5 62.5 to-220 g d s to-220f g d s g d s
fdp12n50nz / fdpf12n50n z ? n-channel unifet tm ii mosfet ?2010 fairchild semiconductor corporation fdp12n50nz / fdpf12n50nz rev. c1 www.fairchildsemi.com 2 package marking and ordering information electrical characteristics t c = 25 o c unless otherwise noted. off characteristics on characteristics dynamic characteristics switching characteristics drain-source diod e characteristics device marking device package reel size tape width quantity fdp12n50nz fdp12n50nz to-220 tube n/a 50 units fdpf12n50nz fdpf12n50nz to-220f tube n/a 50 units symbol parameter test conditions min. typ. max. unit bv dss drain to source breakdown voltage i d = 250 ? a, v gs = 0v, t j = 25 o c 500 --v ? bv dss / ? t j breakdown voltage temperature coefficient i d = 250 ? a, referenced to 25 o c-0.5-v/ o c i dss zero gate voltage drain current v ds = 500v, v gs = 0v - - 1 ? a v ds = 400v, t c = 125 o c--10 i gss gate to body leakage current v gs = 25v, v ds = 0v - - 10 ? a v gs(th) gate threshold voltage v gs = v ds , i d = 250 ? a3.0-5.0v r ds(on) static drain to source on resistance v gs = 10v, i d = 5.75a - 0.46 0.52 ? g fs forward transconductance v ds = 20v, i d = 5.75a - 12 - s c iss input capacitance v ds = 25v, v gs = 0v f = 1mhz - 945 1235 pf c oss output capacitance - 155 205 pf c rss reverse transfer capacitance - 14 20 pf q g total gate charge at 10v v ds = 400v, i d = 11.5a v gs = 10v (note 4) -2330nc q gs gate to source gate charge - 5.5 - nc q gd gate to drain ?miller? charge - 9.6 - nc t d(on) turn-on delay time v dd = 250v, i d = 11.5a r g = 25 ? (note 4) -2050ns t r turn-on rise time - 50 110 ns t d(off) turn-off delay time - 60 130 ns t f turn-off fall time - 45 100 ns i s maximum continuous drain to source diode forward current - - 11.5 a i sm maximum pulsed drain to source diode forward current - - 46 a v sd drain to source diode forward voltage v gs = 0v, i sd = 11.5a - - 1.4 v t rr reverse recovery time v gs = 0v, i sd = 11.5a di f /dt = 100a/ ? s - 315 - ns q rr reverse recovery charge - 2.0 - ? c notes: 1. repetitive rating: pulse width limited by maximum junction temperature 2. l = 8.5mh, i as = 11.5a, v dd = 50v, r g = 25 ? , starting t j = 25 ? c 3. i sd ?? 11.5a, di/dt ? 200a/ ? s, v dd ? bv dss , starting t j = 25 ? c 4. essentially independent of operating temperature typical characteristics
fdp12n50nz / fdpf12n50n z ? n-channel unifet tm ii mosfet ?2010 fairchild semiconductor corporation fdp12n50nz / fdpf12n50nz rev. c1 www.fairchildsemi.com 3 typical characteristics figure 1. on-region characteristics figure 2. transfer characteristics 0.1 1 10 20 0.1 1 10 30 *notes: 1. 250 p s pulse test 2. t c = 25 o c v gs = 15.0 v 10.0 v 8.0 v 7.0 v 6.5v 6.0 v 5.5 v i d , drain current[a] v ds , drain-source voltage[v] 345678910 0.1 1 10 50 -55 o c 150 o c *notes: 1. v ds = 20v 2. 250 p s pulse test 25 o c i d , drain current[a] v gs , gate-source voltage[v] figure 3. on-resistance variation vs. figure 4. body diode forward voltage drain current and gate vo l tage variation vs. source current and temperature 0.4 0.6 0.8 1.0 1.2 1.4 1 10 100 *notes: 1. v gs = 0v 2. 250 p s pulse test 150 o c i s , reverse drain current [a] v sd , body diode forward voltage [v] 25 o c 0 6 12 18 24 30 0.4 0.5 0.6 0.7 0.8 0.9 1.0 *note: t c = 25 o c v gs = 20v v gs = 10v r ds(on) > : @ , drain-source on-resistance i d , drain current [a] figure 5. capacitance characteristics figure 6. gate charge characteristics 0 5 10 15 20 25 0 2 4 6 8 10 *note: i d = 11.5a v ds = 100v v ds = 250v v ds = 400v v gs , gate-source voltage [v] q g , total gate charge [nc] 0.1 1 10 30 0 500 1000 1500 2000 2500 c oss c iss c iss = c gs + c gd c ds = shorted c oss = c ds + c gd c rss = c gd *note: 1. v gs = 0v 2. f = 1mhz c rss capacitances [pf] v ds , drain-source voltage [v]
fdp12n50nz / fdpf12n50n z ? n-channel unifet tm ii mosfet ?2010 fairchild semiconductor corporation fdp12n50nz / fdpf12n50nz rev. c1 www.fairchildsemi.com 4 typical characteristics (continued) figure 7. breakdown voltage variation figure 8. on-resistance variation vs. temperature vs. temperature -100 -50 0 50 100 150 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 *notes: 1. v gs = 0v 2. i d = 250ua bv dss , [normalized] drain-source breakdown voltage t j , junction temperature > o c @ -75 -50 0 50 100 150 0.4 0.8 1.2 1.6 2.0 2.4 2.8 *notes: 1. v gs = 10v 2. i d = 5.75a r ds(on) , [normalized] drain-source on-resistance t j , junction temperature > o c @ f i g u r e 9 . m a x i m u m s a f e o p e r a t i n g a r e a f i g u r e 1 0 . m a x i m u m s a f e o p e r a t i n g a r e a - fdpf12n50nz - fdp12n50nz 1 10 100 1000 0.01 0.1 1 10 100 i d , drain current [a] v ds , drain-source voltage [v] *notes: 1. t c = 25 o c 2. t j = 150 o c 3. single pulse operation in this area is limited by r ds(on) dc 10ms 1ms 100 p s 10 p s 100 ms 1 10 100 1000 0.01 0.1 1 10 100 30 p s 100 p s 1ms 10ms i d , drain current [a] v ds , drain-source voltage [v] operation in this area is limited by r ds(on) * notes : 1. t c = 25 o c 2. t j = 150 o c 3. single pulse dc figure 11. maximum drain current vs. case temp erature 25 50 75 100 125 150 0 2 4 6 8 10 12 i d , drain current [a] t c , case temperature > o c @
fdp12n50nz / fdpf12n50n z ? n-channel unifet tm ii mosfet ?2010 fairchild semiconductor corporation fdp12n50nz / fdpf12n50nz rev. c1 www.fairchildsemi.com 5 typical characteristics (continued) 10 -5 10 -4 10 -3 10 -2 10 -1 110 0.001 0.01 0.1 1 0.01 0.1 0.2 0.05 0.02 * notes : 1. z ? jc (t) = 0.73 o c/w max. 2. duty factor, d=t 1 /t 2 3. t jm - t c = p dm * z ? jc (t) 0.5 single pulse thermal response [ z ? jc ] rectangular pulse duration [sec] 5 10 -5 10 -4 10 -3 10 -2 10 -1 110 10 -2 10 -1 1 5 *notes: 1. z ? jc (t) = 3.0 o c/w max. 2. duty factor, d = t 1 /t 2 3. t jm - t c = p dm * z ? jc (t) single pulse d=0.5 0.02 0.2 0.05 0.1 0.01 z ? jc (t), thermal response t 1 , square wave pulse duration [sec] t 1 p dm t 2 t 1 p dm t 2 figure 13. transient thermal response curve - fdpf12n50nz figure 12. transient thermal response curve - fdp12n50nz z ? jc (t), thermal response [ o c/w] z ? jc (t), thermal response [ o c/w] t 1 , square wave pulse duration [sec] t 1 , square wave pulse duration [sec]
fdp12n50nz / fdpf12n50n z ? n-channel unifet tm ii mosfet ?2010 fairchild semiconductor corporation fdp12n50nz / fdpf12n50nz rev. c1 www.fairchildsemi.com 6 figure 14. gate charge test circuit & waveform figure 15. resistive switch ing test circuit & waveforms figure 16. unclamped inductive switching test circuit & waveforms v gs v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd 10v v ds r l dut r g v gs v gs v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd 10v v ds r l dut r g v gs v gs v gs i g = const.
fdp12n50nz / fdpf12n50n z ? n-channel unifet tm ii mosfet ?2010 fairchild semiconductor corporation fdp12n50nz / fdpf12n50nz rev. c1 www.fairchildsemi.com 7 figure 17. peak diode recovery dv/dt test circuit & waveforms dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- d = gate pulse width gate pulse period --------------------------
fdp12n50nz / fdpf12n50n z ? n-channel unifet tm ii mosfet ?2010 fairchild semiconductor corporation fdp12n50nz / fdpf12n50nz rev. c1 www.fairchildsemi.com 8 mechanical dimensions dimension in millimeters to-220 3l figure 18. to-220, molded, 3lead, jedec variation ab package drawings are provided as a service to customers considering fairchild com ponents. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specif- ically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packag ing area for the most recent package drawings: http://www.fairchildsemi.com/package/packagedetails.html?id=pn_tt220-003
fdp12n50nz / fdpf12n50n z ? n-channel unifet tm ii mosfet ?2010 fairchild semiconductor corporation fdp12n50nz / fdpf12n50nz rev. c1 www.fairchildsemi.com 9 mechanical dimensions dimension in millimeters to-220f 3l figure 19. to220, molded, 3ld, full pack, eiaj sc91, straight lead package drawings are provided as a service to customers considering fairchild com ponents. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specif- ically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packag ing area for the most recent package drawings: http://www.fairchildsemi.com/package/ packagedetails.html?id=pn_tf22s-003
fdp12n50nz / fdpf12n50nz ? n-channel unifet tm ii mosfet ?2010 fairchild semiconductor corporation fdp12n50nz / fdpf12n50nz rev. c1 www.fairchildsemi.com 10 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or desi gn. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditio ns, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical components in life support de vices or systems without the express written approval of fai rchild semiconductor corporation. as used here in: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms accupower? 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